A Solo Coder Brings Vision to a Local LLM as Edge Silicon and TinyML Builders Push Back the Frontier

A Local Multimodal Model Learns to See, No Cloud Involved

On September 1, 2026, Salvatore Sanfilippo — the Redis creator known online as antirez — posted a demo of DeepSeek V4 Flash reading an image on a Mac M5 Max through his own inference engine, DS4 (DwarfStar4). He said Metal support for vision had landed first, with two follow-up patches fixing the CUDA and ROCm builds on August 31, meaning the same multimodal path should run on Apple, NVIDIA, and AMD hardware within hours of the post, according to pasqualepillitteri.it.

The caveat: this is a demo video and commit-log account, not an independent benchmark, and DS4 is deliberately narrow — it runs one model family well rather than trying to be a general llama.cpp-style engine.

Still, DS4 has passed 21,900 GitHub stars since its May 2026 release, and getting a capable multimodal model to run locally across three backends in a matter of days, instead of months, is the actual story: the image never left the machine.

Image Generation, Squeezed Onto a $1 Chip

Developer cpldcpu (Tim) revisited an old side project and got a generative image model running on the RP2350, the microcontroller inside the Raspberry Pi Pico 2, according to a writeup on the builder's own blog. The model and inference code fit under 4MB and the whole thing runs on the dual-core Cortex-M33 using just 520KB of RAM.

The honest caveat: this is a tiny, low-resolution model on a chip that costs about a dollar — nobody is generating photorealistic art here, and the post treats it as a proof of concept rather than a product.

What it demonstrates is how far generative pipelines have been squeezed down the stack: image synthesis, once assumed to need a GPU, now runs on the same silicon that powers keyboard firmware and blinking LEDs.

Qualcomm Widens Its Edge Silicon Line Ahead of IFA

Qualcomm announced the Dragonwing Q-2390 and IQ-2390 processors on September 1, 2026, expanding its edge portfolio toward consumer IoT and industrial gear — retail systems, smart appliances, consumer robots, and machine-vision controllers, per the company's own language reported by TechPowerUp and SmBom.

Qualcomm's VP Jeff Arnold frames the chips as lowering cost and integration barriers for devices that need to "perceive, analyze and act on data locally." That's a vendor pitch, and neither writeup carries independent TOPS figures or shipping benchmarks yet — this is a pre-IFA announcement, not a review.

For the edge-hardware beat, it's another sign that NPU-equipped silicon is moving downmarket, into product categories that previously ran no on-device inference at all.

A Blueprint for Diffusion LLMs on Jetson-Class Hardware

A new arXiv paper posted around September 1, 2026 tackles a specific edge bottleneck: batch-one inference can't amortize weight traffic the way datacenter serving does. The authors propose a co-designed system — wide-I/O LPDDR memory, a low-rank plus INT8-residual KV cache, and drift-mapped FFN weight replacement — mapped onto a mixed-precision systolic array, described in the paper on arXiv.

On modeled Jetson-class platforms running 1.5B and 7B block-diffusion models, they report energy-reduction factors of roughly 3.8x and 4x and latency speedups up to 4.44x, with accuracy drops under one percentage point. These are simulated, self-reported results on an architecture proposal, not shipping silicon or a hardware review.

Still, it's a concrete look at what the next generation of edge inference chips might need to handle diffusion-style LLMs efficiently, rather than just autoregressive ones.

Two ESP32-S3 Builds Push On-Chip Audio Further

Two separate hobby projects posted to r/esp32 this week push audio TinyML forward. One builder, working on keyword spotting as part of a PhD in TinyML, shared a battery-powered desk cat that listens for wake words entirely on an ESP32-S3, no phone or server involved.

A second builder distilled and quantized a neural text-to-speech model to int8 until it fit on an ESP32-S3 (and the cheaper C3), running 5.4 times faster than real time with no internet connection needed.

Both are hobby-scale, self-reported demos rather than published benchmarks against commercial voice assistants. But together they show the on-device voice pipeline — hearing a wake word, speaking a reply — increasingly closing the loop on sub-$10 chips.

Nothing here shipped from a datacenter: a solo engine maintainer, a microcontroller hobbyist, a chipmaker's press release, and two Reddit builders each moved a piece of inference closer to the device doing the work.