Edge Dispatch: Korea's KT Ships a Boxed NPU LLM Station While the ESP32 Crowd Trims Memory Further

KT boxes up a domestic NPU and its own LLM for on-prem deployment

South Korean telecom KT has launched what it calls the NPU LLM Station, an all-in-one appliance running KT's own "Mi:deum K 2.5 Pro" model on Rebellion's ATOM-MAX neural processing unit, according to digitaltoday.co.kr. The pitch is straightforward: enterprises and public agencies that cannot or will not send data to a cloud API get a self-contained box with the model, an operating API layer, and the chip bundled together.

The honest caveat is that this is not phone-in-your-pocket edge AI. It is on-premises inference on dedicated NPU hardware, sitting in a rack or a closet rather than a datacenter, which is a meaningfully different category from cloud inference but still far from a microcontroller or even a laptop. No independent benchmarks of Mi:deum K 2.5 Pro on ATOM-MAX have surfaced yet, and KT's own performance claims should be read as vendor figures until someone outside the company runs them.

It matters for the edge beat because it is another data point in the steady buildout of non-Nvidia NPU silicon paired with domestic language models, joining the Ryzen AI and Snapdragon X pushes already underway. Rebellion has been trying to establish itself as Korea's answer to Western AI chip supply chains, and a shipped, name-attached product is a stronger signal than a roadmap slide.

ESP32 tiny-LLM demo keeps getting leaner: 14.9MB model now runs in about 2MB of working memory

The ongoing effort to run a language model on an $8 ESP32-S3 microcontroller has taken another step, with a technique that keeps most of the 28.9-million-parameter model's weights parked in flash and only pulls a couple of megabytes into active memory during inference, as detailed by theregister.com and the underlying project covered by geeky-gadgets.com. The approach relies on the model's weights being accessed sparingly enough that flash's slow bandwidth stops being the bottleneck it would otherwise be, with output head, embeddings, and KV cache living in PSRAM and activations handled in the chip's 520KB of SRAM.

The self-reported number is 9.88 tokens per second, which the developer notes beats average human reading speed. That is a real, on-device result, but the model is trained on the toy "TinyStories" dataset and produces simple short-story text, not general chat or reasoning. It is a parlor trick with genuine engineering behind it, not a usable assistant.

Why it matters: this is the same llama2.c-derived lineage this beat has tracked for weeks, and each iteration shaving memory footprint further is the actual research question for microcontroller-class inference — not whether a bigger model can be crammed in, but how little RAM a useful-enough model actually needs.

Two different ends of the edge spectrum moved this week: a Korean NPU appliance aimed at enterprise on-prem deployment, and a further-shrunk toy model on an $8 chip. Both are real, both come with caveats worth keeping in mind, and both are linked below.