An NPU-Only Runtime Lands for Ryzen AI as a Vintage Terminal Learns to Think Offline

An NPU-Only Runtime for Ryzen AI's XDNA2

FastFlowLM, a 17MB open-source runtime, lets AMD Ryzen AI laptops run small language models entirely on the XDNA2 neural processing unit, with no load on the GPU. Type flm run llama3.2:1b and the model answers straight from the NPU, with context windows stretching to 256,000 tokens, according to the project's GitHub repo.

These are the developers' own numbers, not an independent benchmark, and FastFlowLM only targets AMD's newest XDNA2 chips — older Ryzen AI silicon and other vendors' NPUs are out of scope. The project is explicitly built as an Ollama-style wrapper for one accelerator rather than a general-purpose engine.

Still, it's a concrete example of a pattern showing up across this week's search results: vendors and independent developers racing to give small transformers a home that isn't a GPU, so the NPU does the quiet work while the discrete graphics card stays free for everything else.

A Vintage Terminal Gets an Offline Brain via Arduino UNO Q

Arduino's own blog describes a build where a decades-old serial terminal is wired to an Arduino UNO Q board running a local language model, so the terminal answers questions with no internet connection at all. The UNO Q's onboard compute handles inference; the vintage hardware just supplies the keyboard and the old CRT-era display, according to the Arduino blog post published on October 1, 2026.

The write-up doesn't give an exact model size or tokens-per-second figure, so treat the "no internet" claim as architecturally true rather than independently benchmarked. But it's a clean demonstration that a free salvaged peripheral plus a sub-$100 board is now enough to host offline inference, not just an echo of a serial port.

Heimr 570M Bets on Speed as Context Grows

Sevren released Heimr 570M, a 570-million-parameter model the company says decodes two to eight times faster than comparably sized open models as context length increases, while scoring above them on its own downstream evaluations, according to the Sevren blog post this week.

Sevren calls Heimr explicitly experimental and says it's sharing early results while the model keeps evolving — that's a self-reported comparison, not a third-party leaderboard entry, and the baseline models used aren't fully itemized in the post. For the small-model crowd, the interesting part isn't the parameter count, it's the long-context decode speed claim, since that's usually where sub-1B models fall apart on real device hardware.

A Reverse-Engineered Toolkit Opens Intel's NPU to Custom C Kernels

A developer working under the handle hsfzxjy published npunlock on GitHub on September 20, 2026 — a project that reconstructs, through reverse engineering rather than any Intel specification, a path from plain C code to a compiled kernel running on the ACT-SHAVE cores inside Intel's NPU3720, the chip found in Meteor Lake-class Core Ultra laptops. Intel's own public stack via OpenVINO exposes only pre-compiled graph-level operators; anything exotic falls back to the CPU or GPU, as detailed in theterminal.space's write-up on the project.

This is unofficial and built against undocumented behavior Intel never published, so it can break with any driver or firmware update. But for developers chasing a custom quantization scheme or an activation function OpenVINO's graph compiler won't accept, it's the first public route to actually programming the vector cores Intel ships silently inside millions of laptop NPUs.

A RISC-V SBC Aims Straight at AI Cameras

CNX Software reports that the Avaota F2 single-board computer, built around Allwinner's new V861 dual-core 64-bit RISC-V SoC, launched October 2, 2026, with 128MB of on-chip DDR3 memory, support for 4K camera input, H.265 video encoding, and built-in PTZ and audio handling aimed squarely at smart-camera builds.

The coverage is based on Allwinner's spec sheet rather than independent testing, and no standalone NPU throughput figure is given — so any claim about running a vision model on the V861 at a given frame rate remains unverified until boards ship to reviewers. Still, it's another data point for how far down the SoC stack AI-camera-specific hardware is reaching, with RISC-V now appearing in commodity camera designs rather than only flagship accelerators.

Five small moves today: an NPU runtime that skips the GPU entirely, an old terminal that stopped needing the internet, a long-context model still finding its footing, a reverse-engineered path into Intel's silicon, and a RISC-V board betting on cameras over desktops. None of it is finished — all of it is worth watching.