A 145B Open LLM Claims a Laptop Seat as Snapdragon's NPU Runs Gemma 4 26B

Edge0 open-sources a 145B model it says runs on a laptop

On November 12, 2026, Edge0 released Edge0-145B and Edge0-120B along with its inference framework and deployment tools. The company calls the 145B model the first open-source on-device model of that size. Its own numbers: 29GB peak memory on a compatible laptop such as a MacBook Pro, 1,100+ tokens/s prefill, 80+ tokens/s decode, about 120W typical power, and 128K to 256K context (edge0.ai). The post reached 282 points on Hacker News.

Treat every figure as self-reported. Edge0 does not name the exact laptop in the part we read, and its own comparison notes say some measurements apply to different models and hardware. The arithmetic is also worth noticing: 29GB for 145B parameters is roughly 1.6 bits per parameter if every weight were resident, so the architecture and compression scheme decide whether this holds up.

If independent runs match the claims, a 120W laptop-class machine doing agentic coding offline would matter. Until then, the open weights and framework are what to test.

Kora OS reports Gemma 4 26B on a Snapdragon X2 Elite NPU

Kora Systems, formerly Playtron and led by Cyanogen co-founder Kirt McMaster, says its Linux desktop OS runs Google's Gemma 4 26B at 25 tokens/s decode and 550 tokens/s prefill with 32K context on the Hexagon NPU of Snapdragon X2 Elite. Chip Dispatch, on November 11, 2026, attributes those figures to McMaster's statements to Tom's Hardware (chipdispatch.com). They are company claims, and McMaster did not specify the RAM configuration or the exact chip.

The notable part is the plumbing. Kora reportedly uses llama.cpp's Hexagon backend and the upstream FastRPC kernel driver, bypassing Qualcomm's own stack. A November 13 summary of llama.cpp releases lists Q5_0 and Q5_1 support for Hexagon with dedicated kernels (k20x.com). Only Qualcomm is supported today. Intel and AMD NPU support is planned, and AMD's NPU is expected to handle embeddings and speech, not language models. The OS is slated for OEM PCs in 2027.

DeepX and Intel sign an MOU to bring a third-party NPU into OpenVINO

DeepX signed a memorandum of understanding with Intel Korea on November 12, 2026 at COEX in Seoul, announced on November 13. The first of four cooperation areas is integrating Intel's OpenVINO with DeepX's NPU, so developers can use existing models and tools on DeepX silicon. The others are physical and edge AI such as robotics, system validation, and next-generation generative AI (asiae.co.kr).

The generative piece is DX-M2, a chip still under development on Samsung's 2nm process, designed to run LLMs and vision-language models at about 5W. Both the chip and the target are plans, not shipping hardware, and the report gives no benchmarks or dates. A separate three-party MOU with server maker KTNF covers on-premises inference servers.

An MOU is not a software release. Watch for an actual OpenVINO plugin or model-conversion tool.

LazyWeights decodes compressed LLM weights on demand for Jetson-class boards

An arXiv paper posted on November 12, 2026 argues that memory decides which LLMs an edge device can run and how fast: capacity on a 4GB Jetson Nano, bandwidth on an 8GB Jetson Orin Nano Super. LazyWeights compresses GPTQ codes losslessly and decodes them on demand between DRAM and L2 cache (arxiv.org).

A daily roundup summarizing the abstract reports models 5.7% to 31.4% smaller than llama.cpp formats, and up to 36% lower latency and 38% lower energy on Orin (k20x.com). Those are the authors' numbers on their chosen models, and the paper is a preprint without independent replication.

Lossless compression is attractive on small boards because output quality stays identical to the GPTQ baseline. The open question is whether it reaches a runtime people actually use.

Vantron shows an i.MX 952 SMARC module for edge vision

At Electronica 2026, Vantron introduced the VT-SBC-SMARC-IMX952, an 82 × 50 mm SMARC 2.1 system-on-module built around NXP's i.MX 952 with two or four Arm Cortex cores. CNX Software's November 13, 2026 report positions it for edge AI vision and industrial HMI (cnx-software.com).

The summary we could read gives no price or ship date, and we did not verify NPU throughput. The "edge AI" label is a market positioning until a datasheet shows what the on-chip accelerator does with real models. The SMARC form factor means a carrier-board swap, not a redesign, for existing industrial designs.

Today's common thread is claims waiting on verification: a 145B model in 29GB, a 26B model on an NPU, and a 2nm chip that does not exist yet. The sources below are where to check the numbers.